A level shift circuit is a device to shift the level of a signal from low voltage to high voltage or vice versa. For example, FIG. 1 shows a conventional level shift circuit 10 to shift a signal from low voltage to high voltage, which includes an input stage 12 and an output stage 14 coupled to each other by nodes N1 and N2: The high level and low level of the input signal VIN are voltages VP1 and VS1, respectively, and after level shift, the high level and low level of the output signal VOUT are voltages VP2 and VS2, respectively. In the input stage 12, when the input signal VIN transits to its high level VP1, an NMOS transistor M5 is turned on and another NMOS transistor M6 is turned off, and consequently the node N1 is electrically connected to a voltage source VS1 and a current I1 is produced to discharge the node N1, thereby pulling down the voltage on the node N1 to a low level. When the voltage on the node N1 transits to the low level, a PMOS transistor M2 is turned on so as to electrically connect the node N2 to a voltage source VP2 and thereby pull high the voltage on the node N2 to the voltage VP2. When the input signal VIN transits to the low level VS1, the NMOS transistor M5 is turned off and the NMOS transistor M6 is turned on, so that the node N2 is electrically connected to the voltage source VS1 and a current I2 is produced to discharge the node N2, thereby pulling down the voltage on the node N2 to a low level. As a result, a PMOS transistor M1 is turned on and thus the node N1 is electrically connected to the voltage source VP2 to pull high the voltage on the node N1 to the voltage VP2. Two high-voltage transistors M3 and M4 are used to prevent excessively large voltage differences between the voltage source VP2 and the nodes N1 and N2, respectively, that may damage the transistors M1 and M2.
In the output stage 14, PMOS transistors M7 and M8 are controlled by the voltages on the nodes N2 and N1, respectively. When the input signal VIN is on the high level VP1, the voltage on the node N1 is at a low level and the voltage on the node N2 is at a high level. Consequently, the PMOS transistor M7 is turned off and the PMOS transistor M8 is turned on, so that a node N4 is electrically connected to the voltage source VP2, and thereby the output signal VOUT will be the voltage VP2. When the input signal VIN is at the low level VS1, the voltage on the node N1 is at a high level and the voltage on the node N2 is at a low level. Consequently, the PMOS transistor M7 is turned on and the PMOS transistor M8 is turned off, so that a node N3 is electrically connected to the voltage source VP2. As a result, an NMOS transistor M10 is turned on to electrically connect the node N4 to a voltage source VS2 and thereby the output signal VOUT will be the voltage VS2.
Since the transistors M3, M4, M5 and M6 in the level shift circuit 10 are all high-voltage devices and thus have large parasitic capacitances, the charge and discharge processes of the nodes N1 and N2 will take very long time. This not only weakens the driving capability of the circuit, but also results in very slow level shift. Moreover, because of the two additional high-voltage PMOS transistors M3 and M4, the level shift circuit 10 has the difficulty with low-voltage applications, which are referred to the applications with small difference between the voltages VP2 and VS1. Hence, if fewer high-voltage transistors are used, the layout will be smaller and the parasitic capacitances will be reduced. Consequently, the driving capability will be improved and the level shift speed is enhanced. Also, low-voltage applications of the circuit are facilitated.
FIG. 2 shows another conventional level shift circuit 20. In the input stage 22 thereof, NMOS transistors MN1 and M′N1 are controlled by input signals SL and S′L, respectively, where the signals SL and S′L are opposite in phase to each other. When the signal SL is high and the signal S′L is low, the NMOS transistor MN1 is turned on to produce a discharge current I1 so as to pull down the voltage on a node S′H to a low level, and thereby a PMOS transistor M′P2 is turned on to pull high the voltage on a node SH to a high level. When the signal SL is low and the signal S′L is high, the NMOS transistor M′N1 is turned on to produce a discharge current I2 so as to pull down the voltage on the node SH to a low level. As a result, a PMOS transistor MP2 is turned on to pull high the voltage on the node S′H to a high level. PMOS transistors MP1 and M′P1 are configured as diodes so as to prevent excessively large voltage differences between the voltage source VDDH and the nodes S′H and SH, respectively. The output stage 24 of the level shift circuit 20 includes serially connected PMOS transistor MP3 and NMOS transistor MN2 controlled by the voltage on the node S′H and the input signal S′L, respectively. When the signal SL is high and the signal S′L is low, the voltage on the node S′H is low, and thus the transistor MP3 is turned on and the transistor MN2 is turned off, thereby asserting a high-level output signal Vout. When the signal SL is low and the signal S′L is high, the voltage on the node S′H is high, and the transistor MP3 is turned off and the transistor MN2 is turned on, thereby asserting a low-level output signal Vout.
In the level shift circuit 20, by using the concept of voltage mirror, the voltage differences between the voltage source VDDH and the nodes SH, S′H are small, and there is thus no need of the high-voltage transistors M3 and M4 in the level shift circuit 10. Therefore, the level shift circuit 20 has less parasitic capacitances and implements quicker level shift. During the transition state where the voltages on the nodes SH and S′H transit from high to low, to enhance the driving capability of the voltage mirror to speed up the level shift, the discharge currents I1 and I2 must be large. However, during the steady state where the voltages on the nodes SH and S′H are remained at high or low, the large currents I1 and I2 will consume much power. If the currents I1 and I2 are decreased for power saving, the driving capability of the voltage mirror will be significantly degraded and the level shift speed will be lowered.
Therefore, it is desired a power saving, high driving capability level shift circuit.